1. Field
Embodiments described herein relate generally to a semiconductor memory device.
2. Description of the Related Art
In recent years, along with a rising level of integration in semiconductor devices, circuit patterns of LSI elements configuring these semiconductor devices are being increasingly miniaturized. Required in this miniaturization of the patterns is not simply a thinning of line width but also an improvement in dimensional accuracy and positioning accuracy of the patterns. Semiconductor memory devices are of no exception to this trend, and there is a continued requirement to fully utilize high precision processing technologies to form memory cells where the certain charge necessary for memory is stored in an ever narrower region of the memory cells.
Conventionally, various kinds of memories such as DRAM, SRAM, and flash memory are manufactured, all of which use a MOSFET as a memory cell. These memories require, along with miniaturization of the patterns, an improvement in dimensional accuracy and positioning accuracy at a rate that exceeds a rate of the miniaturization. The large burden is placed additionally on lithography technology, which is used to form the patterns. Lithography processing costs account for the vast majority of current costs of mass production. The requirement for miniaturization of the patterns is a factor contributing to a rise in lithography processing costs, that is, to a rise in product cost. At the same time, in recent years, a memory known as a resistance varying memory (ReRAM: Resistive RAM) is proposed as a technology for overcoming such problems, a memory cell in the ReRAM being configured by a selection element, which comprises a non-ohmic element typified by a diode, and a resistance varying material. This ReRAM does not utilize storage of a charge in data retention and can be configured without using a MOSFET as a memory cell, and is thus expected to allow high levels of integration exceeding those of conventional trends to be achieved. Arranging the memory cell array of the ReRAM three-dimensionally in stacks makes it possible to realize a large capacity in the ReRAM without increasing cell array area.
Moreover, the ReRAM allows a high density memory cell array to be realized by provision of a cross-point type structure in which a variable resistor and a rectifier such as a diode are disposed at intersections of bit lines and word lines. However, there is a problem with the cross-point type structure of ReRAM utilizing a diode in the memory cell, namely that the sum of reverse leak current when a voltage is applied in a reverse bias direction of the diode gives rise to significantly large power consumption. Furthermore, when a NOR-type structure are adopted by providing a MOSFET to each of the memory cells to reduce power consumption, it becomes impossible to reduce size of the memory cell region to less than 6F2, making it difficult to cut cost per bit.